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Feature: Hazard3 example SoC on Icebreaker support#2113
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…Ts and switching between them automatically
…s quite different to the other platforms
…NFO does anything to avoid unused warnings
…quite different to the other platforms
…a suitable cross file too
…p USB, timing, and setting up the correct vector table address
…lowing pre-commit to run again
…s, reads but erase, write fail
… state machine when in idle already
…ackwards compatibility less ambiguous
* Any delays necessary will exist at callsites * Most platforms do not have this delay * Duration of 10000 iterations depends on Hclk and architecture (stlinkv3 CM7 may complete faster)
The first was that we forgot a `!` on a `calloc` check, the second is we were doing a `CMD_LSC_READ_CRC` vs a `CMD_LSC_RESET_CRC`
It seems to have inexplicably changed? It was 0x5U, but now it's 0x1U? I have no idea what happened.
…he `final_tms` adjustment for `bits` into account
…s in the JTAG chain
…he first device in the chain
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Detailed description
I didn't touch rp2350.c because uniprocessor Hazard3 is unrelated to that (also no flash support and no bootrom) but creating an entire translation unit for this seemed excessive buildsystem-wise.
Tested on 1bitSquared Icebreaker-v1.0e (FT2232H, iCE40UP5k) flashed with https://github.com/Wren6991/Hazard3 modified gateware, and BMDA.
Because progbuf-based memory access is unsupported in BMD, and Abstract Access Memory is not implemented in Hazard3, you need to synthesize with HAVE_SBA=1 (then it doesn't fit 5280 LC so I had to FAST_BRANCHCMP=0 and it also may fail 12 MHz timings, but hit 10 MHz). Also I changed PCF to swap Interface B and Interface A, likewise you can use PMOD 1 or 2 for JTAG DTM and wire up a real BMP that's faster than BMDA+FTDI HS MPSSE (10 KiB/s load/verify).
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